Open role
Senior Design Verification Engineer
A global semiconductor organisation with a design centre in Bengaluru
- LOCATION Bengaluru, Karnataka
- TYPE Permanent
- EXPERIENCE 6–10 years
- REFERENCE VYS-SEM-041
Our client is building out a verification team for a new SoC programme. This is a hands-on senior role with scope to influence methodology, not a headcount fill.
The team is small and the silicon is complex. You would own verification for one or more sub-systems end to end, from testplan through to sign-off.
What you'll do
Responsibilities.
- Own the verification testplan for assigned sub-systems
- Build and extend UVM testbench components and sequences
- Drive coverage closure — functional, code and assertion
- Debug failures with the design team and take them to root cause
- Contribute to methodology and regression infrastructure
What we're looking for
Essential.
- 6+ years in ASIC or SoC design verification
- Strong SystemVerilog and UVM
- Demonstrable coverage-driven verification experience
- At least one silicon tape-out you were personally accountable for
- Comfortable owning debug through to root cause
Nice to have
- Formal verification exposure
- Low-power or UPF verification
- Scripting in Python or Perl for regression tooling
What this role offers
Why it's worth a conversation.
- A sub-system you own outright rather than a slice of someone else's testplan
- A design team in the same building, not across timezones
- Methodology input — this team is still shaping how it works
How to apply
One step.
Send your CV quoting reference VYS-SEM-041. One of our founders reviews every application personally.
Posted 4 August 2026 · Closing 3 October 2026
Let's talk about the team you're building.
Tell us the role, the constraint and the timeline. We'll tell you honestly whether we're the right firm for it — and if we're not, we'll say so.